#ifndef _REGS_H
#define _REGS_H
/*
  author Sylvain Bertrand <digital.ragnarok@gmail.com>
  Protected by GNU Affero GPL v3 with some exceptions.
  See README at root of alga tree.
*/

#define	PCIE_PORT_INDEX				0x38
#define	PCIE_PORT_DATA				0x3c

#define RCU_IDX					0x100
#define RCU_DATA				0x104

#define	VGA_RENDER_CTL				0x300
#define		VGA_VSTATUS_CTL_MASK			0x00030000
#define		VGA_VSTATUS_CTL_CLEAR			0xfffcffff

#define VGA_MEM_BASE_ADDR			0x310
#define VGA_MEM_BASE_ADDR_HIGH			0x324

#define	VGA_HDP_CTL				0x328
#define		VGA_MEM_PAGE_SELECT_EN			BIT(0)
#define		VGA_MEM_DISABLE				BIT(4)
#define		VGA_RBBM_LOCK_DISABLE			BIT(8)
#define		VGA_SOFT_RESET				BIT(16)

#define	D0VGA_CTL				0x330
#define		DVGA_CTL_MODE_ENABLE			BIT(0)
#define		DVGA_CTL_TIMING_SELECT			BIT(8)
#define		DVGA_CTL_SYNC_POLARITY_SELECT		BIT(9)
#define		DVGA_CTL_OVERSCAN_TIMING_SELECT		BIT(10)
#define		DVGA_CTL_OVERSCAN_COLOR_EN		BIT(16)
#define		DVGA_CTL_ROTATE				BIT(24)
#define D1VGA_CTL				0x338
#define D2VGA_CTL                         	0x3e0
#define D3VGA_CTL                         	0x3e4
#define D4VGA_CTL                         	0x3e8
#define D5VGA_CTL                         	0x3ec

#define DMIF_ADDR_CFG				0xbd4

#define	SRBM_STATUS				0xe50
#define 	MC_STATUS_MASK				0x1f00

#define VM_L2_CTL				0x1400
#define		ENABLE_L2_CACHE				BIT(0)
#define		ENABLE_L2_FRAGMENT_PROCESSING		BIT(1)
#define		ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE	BIT(9)
#define		EFFECTIVE_L2_QUEUE_SIZE(x)		(((x) & 7) << 14)
#define VM_L2_CTL2				0x1404
#define		INVALIDATE_ALL_L1_TLBS			BIT(0)
#define		INVALIDATE_L2_CACHE			BIT(1)
#define VM_L2_CTL3				0x1408
#define		BANK_SELECT(x)				((x) << 0)
#define		CACHE_UPDATE_MODE(x)			((x) << 6)

#define	VM_L2_STATUS				0x140c
#define		L2_BUSY					BIT(0)

#define VM_CTX0_CTL				0x1410
#define		ENABLE_CTX				BIT(0)
#define		PT_DEPTH(x)				(((x) & 3) << 1)
#define		RANGE_PROTECTION_FAULT_ENABLE_DEFAULT	BIT(4)
#define VM_CTX1_CTL				0x1414

#define VM_CTX0_REQUEST_RESPONSE		0x1470
#define		REQUEST_TYPE(x)				(((x) & 0xf) << 0)
#define		RESPONSE_TYPE_MASK			0x000000f0
#define		RESPONSE_TYPE_SHIFT			4

#define VM_CTX0_PROTECTION_FAULT_DEFAULT_ADDR	0x1518
#define	VM_CTX0_PT_BASE_ADDR			0x153c
#define	VM_CTX0_PT_END_ADDR			0x157c
#define	VM_CTX0_PT_START_ADDR			0x155c

#define MC_SHARED_CHMAP				0x2004
#define		NOOFCHAN_SHIFT				12
#define		NOOFCHAN_MASK				0x00003000
#define MC_SHARED_CHREMAP			0x2008

#define	MC_VRAM_LOCATION			0x2024 /* 16MB aligned */

#define	MC_AGP_TOP				0x2028 /* 4MB aligned */
#define	MC_AGP_BOT				0x202c /* 4MB aligned */
#define	MC_AGP_BASE				0x2030

#define	MC_VM_SYS_APERTURE_LOW_ADDR		0x2034
#define	MC_VM_SYS_APERTURE_HIGH_ADDR		0x2038
#define	MC_VM_SYS_APERTURE_DEFAULT_ADDR		0x203c

/* MB acronym unknown */
#define	MC_VM_MB_L1_TLB0_CTL			0x2234
#define	MC_VM_MB_L1_TLB1_CTL			0x2238
#define	MC_VM_MB_L1_TLB2_CTL			0x223C
#define	MC_VM_MB_L1_TLB3_CTL			0x2240
#define		ENABLE_L1_TLB					BIT(0)
#define		ENABLE_L1_FRAGMENT_PROCESSING			BIT(1)
#define		SYSTEM_ACCESS_MODE_PA_ONLY			(0 << 3)
#define		SYSTEM_ACCESS_MODE_USE_SYS_MAP			(1 << 3)
#define		SYSTEM_ACCESS_MODE_IN_SYS			(2 << 3)
#define		SYSTEM_ACCESS_MODE_NOT_IN_SYS			(3 << 3)
#define		SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU	(0 << 5)
#define		EFFECTIVE_L1_TLB_SZ(x)				((x)<<15)
#define		EFFECTIVE_L1_QUEUE_SZ(x)			((x)<<18)

/* MD acronym unknown, see MC_VM_MB_L1_TLB*_* regs */
#define	MC_VM_MD_L1_TLB0_CTL			0x2654
#define	MC_VM_MD_L1_TLB1_CTL			0x2658
#define	MC_VM_MD_L1_TLB2_CTL			0x265c

#define	MC_ARB_RAMCFG				0x2760
#define		NOOFBANK_SHIFT					0
#define		NOOFBANK_MASK					0x00000003
#define		NOOFRANK_SHIFT					2
#define		NOOFRANK_MASK					0x00000004
#define		NOOFROWS_SHIFT					3
#define		NOOFROWS_MASK					0x00000038
#define		NOOFCOLS_SHIFT					6
#define		NOOFCOLS_MASK					0x000000c0
#define		CHANSIZE_SHIFT					8 /* 64 or 32 bits */
#define		CHANSIZE_MASK					0x00000100
#define		BURSTLENGTH_SHIFT				9
#define		BURSTLENGTH_MASK				0x00000200
#define		CHANSIZE_OVERRIDE				BIT(11)

#define	HDP_HOST_PATH_CTL			0x2c00
#define	HDP_NONSURFACE_BASE			0x2c04
#define	HDP_NONSURFACE_INFO			0x2c08
#define	HDP_NONSURFACE_SZ			0x2c0c

#define HDP_ADDR_CFG 				0x2f48
#define HDP_MISC_CTL				0x2f4c
#define		HDP_FLUSH_INVALIDATE_CACHE		BIT(0)

/*
 * HDP data
 * 0x2c14 - 0x2f27 32 blocks of 0x18 bytes
 */

#define IH_RB_CTL				0x3e00
#define		IH_RB_ENABLE				BIT(0)
#define		IH_IB_LOG2_DWS(x)			((x) << 1) /* log2 */
#define		IH_RB_FULL_DRAIN_ENABLE			BIT(6)
#define		IH_WPTR_WRITEBACK_ENABLE		BIT(8)
#define		IH_WPTR_WRITEBACK_TIMER(x)		((x) << 9) /* log2 */
#define		IH_WPTR_OVERFLOW_ENABLE			BIT(16)
#define		IH_WPTR_OVERFLOW_CLEAR			BIT(31)
#define IH_RB_BASE				0x3e04
#define IH_RB_RPTR				0x3e08
#define IH_RB_WPTR				0x3e0c
#define		RB_OVERFLOW				BIT(0)
#define		WPTR_OFFSET_MASK			0x3fffc
#define IH_RB_WPTR_ADDR_HI			0x3e10
#define IH_RB_WPTR_ADDR_LO			0x3e14
#define IH_CTL					0x3e18
#define		ENABLE_INTR				BIT(0)
#define		IH_MC_SWAP(x)				((x) << 1)
#define		IH_MC_SWAP_NONE				0
#define		IH_MC_SWAP_16BIT			1
#define		IH_MC_SWAP_32BIT			2
#define		IH_MC_SWAP_64BIT			3
#define		RPTR_REARM				BIT(4)
#define		MC_WRREQ_CREDIT(x)			((x) << 15)
#define		MC_WR_CLEAN_CNT(x)			((x) << 20)

#define RLC_CTL					0x3f00
#define		RLC_ENABLE				BIT(0)
#define RLC_HB_BASE				0x3f10
#define RLC_HB_CTL				0x3f0c
#define RLC_HB_RPTR				0x3f20
#define RLC_HB_WPTR				0x3f1c
#define RLC_HB_WPTR_LSB_ADDR			0x3f14
#define RLC_HB_WPTR_MSB_ADDR			0x3f18
#define RLC_MC_CTL				0x3f44
#define RLC_UCODE_CTL				0x3f48
#define RLC_UCODE_ADDR				0x3f2c
#define RLC_UCODE_DATA				0x3f30

#define	CC_SYS_RB_BACKEND_DISABLE		0x3f88

#define	CGTS_SYS_TCC_DISABLE			0x3f90
#define	CGTS_USER_SYS_TCC_DISABLE		0x3f94

#define RLC_GFX_IDX           			0x3fc4 /* see GRDBM_GFX_IDX */

#define	CFG_MEM_SZ				0x5428 /* unit is MB */

#define INTR_CTL				0x5468
#define		IH_DUMMY_RD_OVERRIDE			BIT(0)
#define		IH_DUMMY_RD_EN				BIT(1)
#define		IH_REQ_NONSNOOP_EN			BIT(3)
#define		GEN_IH_INT_EN				BIT(8)
#define INTR_CTL2				0x546c

#define HDP_MEM_COHERENCY_FLUSH_CTL		0x5480 
#define HDP_REG_COHERENCY_FLUSH_CTL		0x54a0

/*----------------------------------------------------------------------------*/
#define DC_HPD0_INT_STATUS			0x601c
#define DC_HPD0_INT_CTL				0x6020
#define DC_HPD0_CTL				0x6024

#define DC_HPD1_INT_STATUS			0x6028
#define DC_HPD1_INT_CTL				0x602c
#define DC_HPD1_CTL				0x6030

#define DC_HPD2_INT_STATUS			0x6034
#define DC_HPD2_INT_CTL				0x6038
#define DC_HPD2_CTL				0x603c

#define DC_HPD3_INT_STATUS			0x6040
#define DC_HPD3_INT_CTL				0x6044
#define DC_HPD3_CTL				0x6048

#define DC_HPD4_INT_STATUS			0x604c
#define DC_HPD4_INT_CTL				0x6050
#define DC_HPD4_CTL				0x6054

#define DC_HPD5_INT_STATUS			0x6058
#define DC_HPD5_INT_CTL				0x605c
#define DC_HPD5_CTL				0x6060

#define		DC_HPDx_INT_STATUS			BIT(0)
#define		DC_HPDx_INT_STATUS_SENSE		BIT(1)
#define		DC_HPDx_INT_STATUS_RX			BIT(8)

#define		DC_HPDx_INT_CTL_INT_ACK			BIT(0)
#define		DC_HPDx_INT_CTL_INT_POLARITY		BIT(8)
#define		DC_HPDx_INT_CTL_INT_EN			BIT(16)
#define		DC_HPDx_INT_CTL_RX_INT_ACK		BIT(20)
#define		DC_HPDx_INT_CTL_RX_INT_EN		BIT(24)

/* timers are micro seconds */
#define		DC_HPDx_CTL_CONN_TIMER(x)		((x) << 0)
#define		DC_HPDx_CTL_RX_INT_TIMER(x)		((x) << 16)
#define		DC_HPDx_CTL_EN				BIT(28)
/*----------------------------------------------------------------------------*/

#define DISP0_INT_STATUS			0x60f4
#define		LB_D0_VLINE_INT				BIT(2)
#define		LB_D0_VBLANK_INT			BIT(3)
#define		DC_HPD0_INT				BIT(17)
#define		DC_HPD0_RX_INT				BIT(18)
#define		DACA_AUTODETECT_INT			BIT(22)
#define		DACB_AUTODETECT_INT			BIT(23)
#define		DC_I2C_SW_DONE_INT			BIT(24)
#define		DC_I2C_HW_DONE_INT			BIT(25)
#define DISP1_INT_STATUS			0x60f8
#define		LB_D1_VLINE_INT				BIT(2)
#define		LB_D1_VBLANK_INT			BIT(3)
#define		DC_HPD1_INT				BIT(17)
#define		DC_HPD1_RX_INT				BIT(18)
#define		DISP_TIMER_INT				BIT(24)
#define DISP2_INT_STATUS			0x60fc
#define		LB_D2_VLINE_INT				BIT(2)
#define		LB_D2_VBLANK_INT			BIT(3)
#define		DC_HPD2_INT				BIT(17)
#define		DC_HPD2_RX_INT				BIT(18)
#define DISP3_INT_STATUS			0x6100
#define		LB_D3_VLINE_INT				BIT(2)
#define		LB_D3_VBLANK_INT			BIT(3)
#define		DC_HPD3_INT				BIT(17)
#define		DC_HPD3_RX_INT				BIT(18)
#define DISP4_INT_STATUS			0x614c
#define		LB_D4_VLINE_INT				BIT(2)
#define		LB_D4_VBLANK_INT			BIT(3)
#define		DC_HPD4_INT				BIT(17)
#define		DC_HPD4_RX_INT				BIT(18)
#define DISP5_INT_STATUS			0x6150
#define		LB_D5_VLINE_INT				BIT(2)
#define		LB_D5_VBLANK_INT			BIT(3)
#define		DC_HPD5_INT				BIT(17)
#define		DC_HPD5_RX_INT				BIT(18)

#define	DACA_AUTODETECT_INT_CTL			0x66c8
#define	DACB_AUTODETECT_INT_CTL			0x67c8

/*----------------------------------------------------------------------------*/
/* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */
#define CRTC0_REG_OFFSET	(0x6df0 - 0x6df0)
#define CRTC1_REG_OFFSET	(0x79f0 - 0x6df0)
/* many regs here */
#define CRTC2_REG_OFFSET	(0x105f0 - 0x6df0)
#define CRTC3_REG_OFFSET	(0x111f0 - 0x6df0)
#define CRTC4_REG_OFFSET	(0x11df0 - 0x6df0)
#define CRTC5_REG_OFFSET	(0x129f0 - 0x6df0)
/*----------------------------------------------------------------------------*/

/* grph blocks at 0x6800, 0x7400, 0x10000, 0x10c00, 0x11800, 0x12400 */
#define GRPH_ENABLE				0x6800
#define GRPH_CTL				0x6804
#define		GRPH_DEPTH(x)				(((x) & 0x3) << 0)
#define			GRPH_DEPTH_8BPP				0
#define			GRPH_DEPTH_16BPP			1
#define			GRPH_DEPTH_32BPP			2
#define		GRPH_NUM_BANKS(x)			(((x) & 0x3) << 2)
#define			ADDR_SURF_2_BANK			0
#define			ADDR_SURF_4_BANK			1
#define			ADDR_SURF_8_BANK			2
#define			ADDR_SURF_16_BANK			3
#define		GRPH_Z(x)				(((x) & 0x3) << 4)
#define		GRPH_BANK_WIDTH(x)			(((x) & 0x3) << 6)
#define			ADDR_SURF_BANK_WIDTH_1			0
#define			ADDR_SURF_BANK_WIDTH_2			1
#define			ADDR_SURF_BANK_WIDTH_4			2
#define			ADDR_SURF_BANK_WIDTH_8			3
#define		GRPH_FMT(x)				(((x) & 0x7) << 8)
			/* 8 bpp */
#define			GRPH_FMT_INDEXED			0
			/* 16 bpp */
#define			GRPH_FMT_ARGB1555			0
#define			GRPH_FMT_ARGB565			1
#define			GRPH_FMT_ARGB4444			2
#define			GRPH_FMT_AI88				3
#define			GRPH_FMT_MONO16				4
#define			GRPH_FMT_BGRA5551			5
			/* 32 bpp */
#define			GRPH_FMT_ARGB8888			0
#define			GRPH_FMT_ARGB2101010			1
#define			GRPH_FMT_32BPP_DIG			2
#define			GRPH_FMT_8B_ARGB2101010			3
#define			GRPH_FMT_BGRA1010102			4
#define			GRPH_FMT_8B_BGRA1010102			5
#define			GRPH_FMT_RGB111110			6
#define			GRPH_FMT_BGR101111			7
#define		GRPH_BANK_HEIGHT(x)			(((x) & 0x3) << 11)
#define			ADDR_SURF_BANK_HEIGHT_1			0
#define			ADDR_SURF_BANK_HEIGHT_2			1
#define			ADDR_SURF_BANK_HEIGHT_4			2
#define			ADDR_SURF_BANK_HEIGHT_8			3
#define		GRPH_TILE_SPLIT(x)			(((x) & 0x7) << 13)
#define			ADDR_SURF_TILE_SPLIT_64B		0
#define			ADDR_SURF_TILE_SPLIT_128B		1
#define			ADDR_SURF_TILE_SPLIT_256B		2
#define			ADDR_SURF_TILE_SPLIT_512B		3
#define			ADDR_SURF_TILE_SPLIT_1KB		4
#define			ADDR_SURF_TILE_SPLIT_2KB		5
#define			ADDR_SURF_TILE_SPLIT_4KB		6
#define		GRPH_MACRO_TILE_ASPECT(x)		(((x) & 0x3) << 18)
#define			ADDR_SURF_MACRO_TILE_ASPECT_1		0
#define			ADDR_SURF_MACRO_TILE_ASPECT_2		1
#define			ADDR_SURF_MACRO_TILE_ASPECT_4		2
#define			ADDR_SURF_MACRO_TILE_ASPECT_8		3
#define		GRPH_ARRAY_MODE(x)			(((x) & 0x7) << 20)
#define			GRPH_ARRAY_LINEAR_GENERAL		0
#define			GRPH_ARRAY_LINEAR_ALIGNED		1
#define			GRPH_ARRAY_1D_TILED_THIN1		2
#define			GRPH_ARRAY_2D_TILED_THIN1		4
#define GRPH_SWAP_CTL				0x680c
#define		GRPH_ENDIAN_SWAP(x)			(((x) & 0x3) << 0)
#define			GRPH_ENDIAN_NONE			0
#define			GRPH_ENDIAN_8IN16			1
#define			GRPH_ENDIAN_8IN32			2
#define			GRPH_ENDIAN_8IN64			3
#define		GRPH_RED_CROSSBAR(x)			(((x) & 0x3) << 4)
#define			GRPH_RED_SEL_R				0
#define			GRPH_RED_SEL_G				1
#define			GRPH_RED_SEL_B				2
#define			GRPH_RED_SEL_A				3
#define		GRPH_GREEN_CROSSBAR(x)			(((x) & 0x3) << 6)
#define			GRPH_GREEN_SEL_G			0
#define			GRPH_GREEN_SEL_B			1
#define			GRPH_GREEN_SEL_A			2
#define			GRPH_GREEN_SEL_R			3
#define		GRPH_BLUE_CROSSBAR(x)			(((x) & 0x3) << 8)
#define			GRPH_BLUE_SEL_B				0
#define			GRPH_BLUE_SEL_A				1
#define			GRPH_BLUE_SEL_R				2
#define			GRPH_BLUE_SEL_G				3
#define		GRPH_ALPHA_CROSSBAR(x)			(((x) & 0x3) << 10)
#define			GRPH_ALPHA_SEL_A			0
#define			GRPH_ALPHA_SEL_R			1
#define			GRPH_ALPHA_SEL_G			2
#define			GRPH_ALPHA_SEL_B			3
#define GRPH_PRIMARY_SURFACE_ADDR		0x6810
#define GRPH_SECONDARY_SURFACE_ADDR		0x6814
#define		GRPH_DFQ_ENABLE				BIT(0)
#define		GRPH_SURFACE_ADDR_MASK			0xffffff00
#define GRPH_PITCH				0x6818
#define GRPH_PRIMARY_SURFACE_ADDR_HIGH		0x681c
#define GRPH_SECONDARY_SURFACE_ADDR_HIGH	0x6820
#define GRPH_SURFACE_OFFSET_X			0x6824
#define GRPH_SURFACE_OFFSET_Y			0x6828
#define GRPH_X_START				0x682c
#define GRPH_Y_START				0x6830
#define GRPH_X_END				0x6834
#define GRPH_Y_END				0x6838
#define GRPH_UPDATE				0x6844
#define		GRPH_SURFACE_UPDATE_PENDING		BIT(2)
#define		GRPH_UPDATE_LOCK			BIT(16)
#define GRPH_FLIP_CTL				0x6848
#define		GRPH_SURFACE_UPDATE_H_RETRACE_EN	BIT(0)

/* 0x6858 ... */
#define GRPH_INT_STATUS				0x6858
#define		GRPH_PFLIP_INT_OCCURRED			BIT(0)
#define		GRPH_PFLIP_INT_CLEAR			BIT(8)

/* 0x685c ... */
#define	GRPH_INT_CTL				0x685c
#define		GRPH_PFLIP_INT_MASK			BIT(0)
#define		GRPH_PFLIP_INT_TYPE			BIT(8)

/* 0x69e0 ... */
#define LUT_RW_MODE				0x69e0
#define LUT_RW_IDX				0x69e4
#define LUT_30_COLOR				0x69f0
#define LUT_WRITE_EN_MASK			0x69f8
#define LUT_CTL					0x6a00
#define LUT_BLACK_OFFSET_BLUE			0x6a04
#define LUT_BLACK_OFFSET_GREEN			0x6a08
#define LUT_BLACK_OFFSET_RED			0x6a0c
#define LUT_WHITE_OFFSET_BLUE			0x6a10
#define LUT_WHITE_OFFSET_GREEN			0x6a14
#define LUT_WHITE_OFFSET_RED			0x6a18

/* 0x6b04 ... */
#define DESKTOP_HEIGHT				0x6b04
#define VLINE_START_END				0x6b08

/* 0x6b40 ... */
#define INT_MASK				0x6b40
#define		VBLANK_INT_MASK				BIT(0)
#define		VLINE_INT_MASK				BIT(4)

/* 0x6bb8 ... */
#define VLINE_STATUS				0x6bb8
#define		VLINE_OCCURRED				BIT(0)
#define		VLINE_ACK				BIT(4)
#define		VLINE_STAT				BIT(12)
#define		VLINE_INT				BIT(16)
#define		VLINE_INT_TYPE				BIT(17)

/* 0x6bbc ... */
#define VBLANK_STATUS				0x6bbc
#define		VBLANK_OCCURRED				BIT(0)
#define		VBLANK_ACK				BIT(4)
#define		VBLANK_STAT				BIT(12)
#define		VBLANK_INT				BIT(16)
#define		VBLANK_INT_TYPE				BIT(17)

#define VIEWPORT_START				0x6d70
#define VIEWPORT_SZ				0x6d74

/* 0x6e70 ... */
#define CRTC_CTL				0x6e70
#define		CRTC_MASTER_EN				BIT(0)
#define		CRTC_DISP_READ_REQUEST_DISABLE		BIT(24)
#define CRTC_UPDATE_LOCK			0x6ed4
#define MASTER_UPDATE_MODE			0x6ef8

#define	GRBM_CTL				0x8000
#define		GRBM_READ_TIMEOUT(x)			((x) << 0)
#define	GRBM_STATUS				0x8010
#define		CMDFIFO_AVAIL_MASK			0x0000000f
#define		SRBM_RQ_PENDING				BIT(5)
#define		CF_RQ_PENDING				BIT(7)
#define		PF_RQ_PENDING				BIT(8)
#define		GRBM_EE_BUSY				BIT(10)
#define		SX_CLEAN				BIT(11)
#define		DB_CLEAN				BIT(12)
#define		CB_CLEAN				BIT(13)
#define		TA_BUSY 				BIT(14)
#define		VGT_BUSY_NO_DMA				BIT(16)
#define		VGT_BUSY				BIT(17)
#define		SX_BUSY 				BIT(20)
#define		SH_BUSY 				BIT(21)
#define		SPI_BUSY				BIT(22)
#define		SC_BUSY 				BIT(24)
#define		PA_BUSY 				BIT(25)
#define		DB_BUSY 				BIT(26)
#define		CP_COHERENCY_BUSY      			BIT(28)
#define		CP_BUSY 				BIT(29)
#define		CB_BUSY 				BIT(30)
#define		GUI_ACTIVE				BIT(31)
#define	GRBM_STATUS_SE0				0x8014
#define	GRBM_STATUS_SE1				0x8018
#define		SE_SX_CLEAN				BIT(0)
#define		SE_DB_CLEAN				BIT(1)
#define		SE_CB_CLEAN				BIT(2)
#define		SE_TA_BUSY				BIT(25)
#define		SE_SX_BUSY				BIT(26)
#define		SE_SPI_BUSY				BIT(27)
#define		SE_SH_BUSY				BIT(28)
#define		SE_SC_BUSY				BIT(29)
#define		SE_DB_BUSY				BIT(30)
#define		SE_CB_BUSY				BIT(31)

#define	GRBM_SOFT_RESET				0x8020
#define		SOFT_RESET_CP				BIT(0)
#define		SOFT_RESET_CB				BIT(1)
#define		SOFT_RESET_DB				BIT(3)
#define		SOFT_RESET_PA				BIT(5)
#define		SOFT_RESET_SC				BIT(6)
#define		SOFT_RESET_SPI				BIT(8)
#define		SOFT_RESET_SH				BIT(9)
#define		SOFT_RESET_SX				BIT(10)
#define		SOFT_RESET_TC				BIT(11)
#define		SOFT_RESET_TA				BIT(12)
#define		SOFT_RESET_VC				BIT(13)
#define		SOFT_RESET_VGT				BIT(14)

#define GRBM_GFX_IDX				0x802c
#define		INSTANCE_IDX(x)				((x) << 0)
#define		SE_IDX(x)				((x) << 16)
#define		INSTANCE_BROADCAST_WRITES		BIT(30)
#define		SE_BROADCAST_WRITES			BIT(31)

#define GRBM_INT_CTL				0x8060
#define		RDERR_INT_ENABLE			BIT(0)
#define		GUI_IDLE_INT_ENABLE			BIT(19)

/* not yet used in the code
#define	SCRATCH_REG0	0x8500
#define	SCRATCH_REG1	0x8504
#define	SCRATCH_REG2	0x8508
#define	SCRATCH_REG3	0x850c
#define	SCRATCH_REG4	0x8510
#define	SCRATCH_REG5	0x8514
#define	SCRATCH_REG6	0x8518
#define	SCRATCH_REG7	0x851c
*/
#define	SCRATCH_UMSK				0x8540
#define	SCRATCH_ADDR				0x8544

#define	CP_SEM_WAIT_TIMER			0x85bc

#define CP_ME_CTL				0x86d8
#define		CP_ME_HALT				BIT(28)
#define		CP_PFP_HALT				BIT(26)

#define	CP_RB_RPTR				0x8700
#define	CP_RB_WPTR_DELAY			0x8704

#define	CP_QUEUE_THRESHOLDS			0x8760
#define		ROQ_IB1_START(x)			((x) << 0)
#define		ROQ_IB2_START(x)			((x) << 8)

#define CP_MEQ_THRESHOLDS			0x8764
#define		STQ_SPLIT(x)				((x) << 0)

#define	CP_PERFMON_CTL				0x87fc

#define	VGT_CACHE_INVALIDATION			0x88c4
#define		CACHE_INVALIDATION(x)			((x) << 0)
#define			VC_ONLY					0
#define			TC_ONLY					1
#define			VC_AND_TC				2
#define		AUTO_INVLD_EN(x)			((x) << 6)
#define			NO_AUTO					0
#define			ES_AUTO					1
#define			GS_AUTO					2
#define			ES_AND_GS_AUTO				3

#define	VGT_GS_VERTEX_REUSE			0x88d4

#define CC_GC_SHADER_PIPE_CFG			0x8950
#define		WRITE_DIS				BIT(0)
#define	GC_USER_SHADER_PIPE_CFG			0x8954
#define		INACTIVE_QD_PIPES(x)			((x) << 8)
#define		INACTIVE_QD_PIPES_MASK			0x0000ff00
#define		INACTIVE_SIMDS(x)			((x) << 16)
#define		INACTIVE_SIMDS_MASK			0x00ff0000

#define	VGT_NUM_INSTS				0x8974

#define	PA_CL_ENHANCE				0x8a14
#define		CLIP_VTX_REORDER_ENA			BIT(0)
#define		NUM_CLIP_SEQ(x)				((x) << 1)

#define	PA_SU_LINE_STIPPLE_VALUE		0x8a60
#define	PA_SC_LINE_STIPPLE_STATE		0x8b10

#define	PA_SC_FORCE_EOV_MAX_CNTS		0x8b24
#define		FORCE_EOV_MAX_CLK_CNT(x)		((x) << 0)
#define		FORCE_EOV_MAX_REZ_CNT(x)		((x) << 16)

#define	PA_SC_FIFO_SZ				0x8bcc
#define		SC_PRIM_FIFO_SZ(x)			((x) << 0)
#define		SC_HIZ_TILE_FIFO_SZ(x)			((x) << 12)
#define		SC_EARLYZ_TILE_FIFO_SZ(x)		((x) << 20)

#define	SQ_CFG					0x8c00
#define		VC_ENABLE				BIT(0)
#define		EXPORT_SRC_C				BIT(1)
#define		CS_PRIO(x)				((x) << 18)
#define		LS_PRIO(x)				((x) << 20)
#define		HS_PRIO(x)				((x) << 22)
#define		PS_PRIO(x)				((x) << 24)
#define		VS_PRIO(x)				((x) << 26)
#define		GS_PRIO(x)				((x) << 28)
#define		ES_PRIO(x)				((x) << 30)

#define	SQ_GPR_RES_MGMT_1			0x8c04
#define		NUM_PS_GPRS(x)				((x) << 0)
#define		NUM_VS_GPRS(x)				((x) << 16)
#define		NUM_CLAUSE_TEMP_GPRS(x)			((x) << 28)

#define	SQ_GPR_RES_MGMT_2			0x8c08
#define		NUM_GS_GPRS(x)				((x) << 0)
#define		NUM_ES_GPRS(x)				((x) << 16)

#define	SQ_GPR_RES_MGMT_3			0x8c0c
#define		NUM_HS_GPRS(x)				((x) << 0)
#define		NUM_LS_GPRS(x)				((x) << 16)

#define	SQ_THD_RES_MGMT				0x8c18
#define		NUM_PS_THDS(x)				((x) << 0)
#define		NUM_VS_THDS(x)				((x) << 8)
#define		NUM_GS_THDS(x)				((x) << 16)
#define		NUM_ES_THDS(x)				((x) << 24)

#define	SQ_THD_RES_MGMT_2			0x8c1c
#define		NUM_HS_THDS(x)				((x) << 0)
#define		NUM_LS_THDS(x)				((x) << 8)

#define	SQ_STACK_RES_MGMT_1			0x8c20
#define		NUM_PS_STACK_ENTRIES(x)			((x) << 0)
#define		NUM_VS_STACK_ENTRIES(x)			((x) << 16)

#define	SQ_STACK_RES_MGMT_2			0x8c24
#define		NUM_GS_STACK_ENTRIES(x)			((x) << 0)
#define		NUM_ES_STACK_ENTRIES(x)			((x) << 16)

#define	SQ_STACK_RES_MGMT_3			0x8c28
#define		NUM_HS_STACK_ENTRIES(x)			((x) << 0)
#define		NUM_LS_STACK_ENTRIES(x)			((x) << 16)

#define	SQ_MS_FIFO_SZS				0x8cf0
#define		CACHE_FIFO_SZ(x)			((x) << 0)
#define		FETCH_FIFO_HIWATER(x)			((x) << 8)
#define		DONE_FIFO_HIWATER(x)			((x) << 16)
#define		ALU_UPDATE_FIFO_HIWATER(x)		((x) << 24)

#define	SQ_DYN_GPR_CTL_PS_FLUSH_REQ 	   	0x8d8c

#define	SQ_LDS_RES_MGMT				0x8e2c

#define	SX_EXPORT_BUF_SZS			0x900C
#define		COLOR_BUF_SZ(x)				((x) << 0)
#define		POSITION_BUF_SZ(x)			((x) << 8)
#define		SMX_BUF_SZ(x)				((x) << 16)

#define	SX_DEBUG_1				0x9058
#define		ENABLE_NEW_SMX_ADDR			BIT(16)

#define	SPI_CFG_CTL				0x9100
#define		GPR_WRITE_PRIORITY(x)			((x) << 0)
#define	SPI_CFG_CTL_1				0x913c
#define		VTX_DONE_DELAY(x)			((x) << 0)
#define		INTERP_ONE_PRIM_PER_ROW			BIT(4)

#define	CGTS_TCC_DISABLE			0x9148
#define	CGTS_USER_TCC_DISABLE			0x914c

#define	TA_CTL_AUX				0x9508
#define		DISABLE_CUBE_WRAP			BIT(0)
#define		DISABLE_CUBE_ANISO			BIT(1)
#define		SYNC_GRADIENT				BIT(24)
#define		SYNC_WALKER				BIT(25)
#define		SYNC_ALIGNER				BIT(26)

#define	TCP_CHAN_STEER_LO			0x960c
#define	TCP_CHAN_STEER_HI			0x9610

#define CC_RB_BACKEND_DISABLE			0x98f4
#define		BACKEND_DISABLE(x)			((x) << 16)

#define GB_ADDR_CFG				0x98f8
#define		NUM_PIPES(x)				((x) << 0)
#define		PIPE_INTERLEAVE_SZ(x)			((x) << 4)
#define		BANK_INTERLEAVE_SZ(x)			((x) << 8)
#define		NUM_SES(x)				((x) << 12)
#define		SE_TILE_SZ(x)				((x) << 16)
#define		NUM_GPUS(x)				((x) << 20)
#define		MULTI_GPU_TILE_SZ(x)			((x) << 24)
#define		ROW_SZ_MASK				0x30000000
#define		ROW_SZ_SHIFT				28
#define		ROW_SZ(x)				((x) << ROW_SZ_SHIFT)

#define GB_BACKEND_MAP  			0x98fc

#define CB_PERF_CTR0_SEL_0			0x9a20
#define CB_PERF_CTR0_SEL_1			0x9a24
#define CB_PERF_CTR1_SEL_0			0x9a28
#define CB_PERF_CTR1_SEL_1			0x9a2c
#define CB_PERF_CTR2_SEL_0			0x9a30
#define CB_PERF_CTR2_SEL_1			0x9a34
#define CB_PERF_CTR3_SEL_0			0x9a38
#define CB_PERF_CTR3_SEL_1			0x9a3c

#define	GC_USER_RB_BACKEND_DISABLE		0x9b7c

#define	SMX_DC_CTL0				0xa020
#define		USE_HASH_FUNCTION			BIT(0)
#define		NUMBER_OF_SETS(x)			((x) << 1)
#define		FLUSH_ALL_ON_EVENT			BIT(10)
#define		STALL_ON_EVENT				BIT(11)

#define	CP_RB_BASE				0xc100
#define	CP_RB_CTL				0xc104
#define		RB_BUF_LOG2_QWS(x)			((x) << 0) /* log2 */
#define		RB_BLK_LOG2_QWS(x)			((x) << 8) /* log2 */
#define		RB_NO_UPDATE				BIT(27)
#define		RB_RPTR_WR_ENA				BIT(31)
#define		BUF_SWAP_32BIT				BIT(16)

#define	CP_RB_RPTR_WR				0xc108
#define	CP_RB_RPTR_ADDR				0xc10c
#define		RB_RPTR_SWAP(x)				((x) << 0)
#define	CP_RB_RPTR_ADDR_HI			0xc110
#define	CP_RB_WPTR				0xc114

#define CP_INT_CTL				0xc124
#define		CNTX_BUSY_INT_ENABLE			BIT(19)
#define		CNTX_EMPTY_INT_ENABLE			BIT(20)
#define		SCRATCH_INT_ENABLE			BIT(25)
#define		TIME_STAMP_INT_ENABLE			BIT(26)
#define		IB2_INT_ENABLE				BIT(29)
#define		IB1_INT_ENABLE				BIT(30)
#define		RB_INT_ENABLE				BIT(31)
#define CP_INT_STATUS				0xc128
#define		SCRATCH_INT_STAT			BIT(25)
#define		TIME_STAMP_INT_STAT			BIT(26)
#define		IB2_INT_STAT				BIT(29)
#define		IB1_INT_STAT				BIT(30)

#define	CP_PFP_UCODE_ADDR			0xc150
#define	CP_PFP_UCODE_DATA			0xc154
#define		RB_INT_STAT				BIT(31)

#define	CP_ME_RAM_RADDR				0xc158
#define	CP_ME_RAM_WADDR				0xc15C
#define	CP_ME_RAM_DATA				0xc160

#define	CP_DEBUG				0xc1fc

/* from there we must use indirect MMIO because above reg MMIO size */

#define SQ_ALU_CONST_BUF_SZ_PS_0		0x28140

#define	VGT_VERTEX_REUSE_BLOCK_CTL		0x28c58
#define		VTX_REUSE_DEPTH_MASK			0x000000ff
#define	VGT_OUT_DEALLOC_CTL			0x28c5c
#define		DEALLOC_DIST_MASK			0x0000007f

#define	CB_COLOR0_BASE				0x28c60
#define	CB_COLOR1_BASE				0x28c9c
#define	CB_COLOR2_BASE				0x28cd8
#define	CB_COLOR3_BASE				0x28d14
#define	CB_COLOR4_BASE				0x28d50
#define	CB_COLOR5_BASE				0x28d8c
#define	CB_COLOR6_BASE				0x28dc8
#define	CB_COLOR7_BASE				0x28e04
#define	CB_COLOR8_BASE				0x28e40
#define	CB_COLOR9_BASE				0x28e5c
#define	CB_COLOR10_BASE				0x28e78
#define	CB_COLOR11_BASE				0x28e94

#define SQ_ALU_CONST_BUF_SZ_HS_0		0x28f80

static u32 regs_hpd_int_status[CRTCS_N_MAX] __attribute__ ((unused)) = {
	DC_HPD0_INT_STATUS,
	DC_HPD1_INT_STATUS,
	DC_HPD2_INT_STATUS,
	DC_HPD3_INT_STATUS,
	DC_HPD4_INT_STATUS,
	DC_HPD5_INT_STATUS
};

static u32 regs_hpd_int_ctl[CRTCS_N_MAX] __attribute__ ((unused)) = {
	DC_HPD0_INT_CTL,
	DC_HPD1_INT_CTL,
	DC_HPD2_INT_CTL,
	DC_HPD3_INT_CTL,
	DC_HPD4_INT_CTL,
	DC_HPD5_INT_CTL
};

static u32 regs_hpd_ctl[CRTCS_N_MAX] __attribute__ ((unused)) = {
	DC_HPD0_CTL,
	DC_HPD1_CTL,
	DC_HPD2_CTL,
	DC_HPD3_CTL,
	DC_HPD4_CTL,
	DC_HPD5_CTL
};

static u32 regs_crtc_int_mask[CRTCS_N_MAX] __attribute__ ((unused)) = {
	INT_MASK + CRTC0_REG_OFFSET,
	INT_MASK + CRTC1_REG_OFFSET,
	INT_MASK + CRTC2_REG_OFFSET,
	INT_MASK + CRTC3_REG_OFFSET,
	INT_MASK + CRTC4_REG_OFFSET,
	INT_MASK + CRTC5_REG_OFFSET
};

static u32 regs_crtc_grph_int_ctl[CRTCS_N_MAX] __attribute__ ((unused)) = {
	GRPH_INT_CTL + CRTC0_REG_OFFSET,
	GRPH_INT_CTL + CRTC1_REG_OFFSET,
	GRPH_INT_CTL + CRTC2_REG_OFFSET,
	GRPH_INT_CTL + CRTC3_REG_OFFSET,
	GRPH_INT_CTL + CRTC4_REG_OFFSET,
	GRPH_INT_CTL + CRTC5_REG_OFFSET
};

static u32 regs_disp_int_status[CRTCS_N_MAX] __attribute__ ((unused)) = {
	DISP0_INT_STATUS,
	DISP1_INT_STATUS,
	DISP2_INT_STATUS,
	DISP3_INT_STATUS,
	DISP4_INT_STATUS,
	DISP5_INT_STATUS
};

static u32 regs_crtc_grph_int_status[CRTCS_N_MAX] __attribute__ ((unused)) = {
	GRPH_INT_STATUS + CRTC0_REG_OFFSET,
	GRPH_INT_STATUS + CRTC1_REG_OFFSET,
	GRPH_INT_STATUS + CRTC2_REG_OFFSET,
	GRPH_INT_STATUS + CRTC3_REG_OFFSET,
	GRPH_INT_STATUS + CRTC4_REG_OFFSET,
	GRPH_INT_STATUS + CRTC5_REG_OFFSET
};

static u32 regs_crtc_vblank_status[CRTCS_N_MAX] __attribute__ ((unused)) = {
	VBLANK_STATUS + CRTC0_REG_OFFSET,
	VBLANK_STATUS + CRTC1_REG_OFFSET,
	VBLANK_STATUS + CRTC2_REG_OFFSET,
	VBLANK_STATUS + CRTC3_REG_OFFSET,
	VBLANK_STATUS + CRTC4_REG_OFFSET,
	VBLANK_STATUS + CRTC5_REG_OFFSET
};

static u32 regs_crtc_vline_status[CRTCS_N_MAX] __attribute__ ((unused)) = {
	VLINE_STATUS + CRTC0_REG_OFFSET,
	VLINE_STATUS + CRTC1_REG_OFFSET,
	VLINE_STATUS + CRTC2_REG_OFFSET,
	VLINE_STATUS + CRTC3_REG_OFFSET,
	VLINE_STATUS + CRTC4_REG_OFFSET,
	VLINE_STATUS + CRTC5_REG_OFFSET
};

static u32 vals_hpd_int[CRTCS_N_MAX] __attribute__ ((unused)) = {
	DC_HPD0_INT,
	DC_HPD1_INT,
	DC_HPD2_INT,
	DC_HPD3_INT,
	DC_HPD4_INT,
	DC_HPD5_INT
};

static u32 vals_lb_d_vblank_int[CRTCS_N_MAX] __attribute__ ((unused)) = {
	LB_D0_VBLANK_INT,
	LB_D1_VBLANK_INT,
	LB_D2_VBLANK_INT,
	LB_D3_VBLANK_INT,
	LB_D4_VBLANK_INT,
	LB_D5_VBLANK_INT
};

static u32 vals_lb_d_vline_int[CRTCS_N_MAX] __attribute__ ((unused)) = {
	LB_D0_VLINE_INT,
	LB_D1_VLINE_INT,
	LB_D2_VLINE_INT,
	LB_D3_VLINE_INT,
	LB_D4_VLINE_INT,
	LB_D5_VLINE_INT
};

static u32 vals_crtc_offset[CRTCS_N_MAX] __attribute__ ((unused)) = {
	CRTC0_REG_OFFSET,
	CRTC1_REG_OFFSET,
	CRTC2_REG_OFFSET,
	CRTC3_REG_OFFSET,
	CRTC4_REG_OFFSET,
	CRTC5_REG_OFFSET
};

static u32 regs_vga_ctl[CRTCS_N_MAX] __attribute__ ((unused)) = {
	D0VGA_CTL,
	D1VGA_CTL,
	D2VGA_CTL,
	D3VGA_CTL,
	D4VGA_CTL,
	D5VGA_CTL
};
#endif /* _REGS_H */
